Values stored in the bitcells of a memory device may be retained when the memory device goes into a retention mode, in which the device shuts down into a low power mode to reduce its power consumption whilst it is not in active use and then later returns to an active data processing mode in which the data values retained during the retention mode can once again be accessed and processed. This may for example be supported by providing the memory device with a power gating switch enabling the bitcells of the memory device to be coupled to and decoupled from a power rail. For example an SRAM memory device may be put into a retention mode in which, whilst not operationally accessible, the memory content is nevertheless retained by all bitcells of the RAM by means of such coupling being enabled.